1. Field
The embodiments described herein relate to an electrically rewritable nonvolatile semiconductor memory device and operating method thereof.
2. Description of the Related Art
A memory cell array in a NAND-type flash memory is configured as an arrangement of NAND cell units, each of the NAND cell units having a plurality of memory cells connected in series. Each end of a NAND cell unit is connected to, respectively, a bit line and a source line, via select gate transistors. The control gate electrodes CG of memory cells in each NAND cell unit are connected to different word lines. In each NAND cell unit, a plurality of memory cells are connected in series, sharing a source and a drain with each other. In NAND-type flash memory, these memory cells share select gate transistors, associated bit-line or source-line contacts, and so on. This may reduce the size of a unit memory cell. Furthermore, device regions for word lines, memory cells, and so on, in the NAND-type flash memory are configured close to a simple stripe pattern. This is suitable for shrinking and allows large capacity flash memory to be realized.
In NAND-type flash memory, data write and erase are performed by causing FN tunnel current to flow through many cells at the same time. Specifically, data write is performed on a page basis, where a set of memory cells sharing one word line represents one page. After a data write operation, a verify read (write verify) operation is performed to verify whether data is accurately written to the memory cells or not. As a result of the write verify operation, if data is not written to the memory cells satisfactorily, then similar write operations and write verify operations are repeated, raising a write pulse voltage in stages (step-up).
In addition, data erase in NAND-type flash memory is performed on a block basis, where a block is defined as a set of NAND cell units sharing a word line and a select gate line. In addition, when data erase is performed on a block basis in the NAND-type flash memory, a verify read (erase verify) operation is performed to verify whether a memory cell is achieved an erase state or not, that is, whether a threshold voltage of the memory cell falls within a certain range or not. As a result of the erase verify operation, if erase is not performed satisfactorily, then similar erase operations and erase verify operations are repeated, raising an erase voltage in stages (step-up).
Incidentally, when the write operation is performed on one selected memory cell stepping up the write pulse voltage, an intermediate voltage applied to unselected memory cells is also stepped up in some cases. At this case, due to effects of the intermediate voltage, an excessive charge is injected into the selected memory cell. In case an excessive charge is injected into the selected memory cell, the threshold voltage changes more than a desired value, with the result that data cannot be accurately written in the NAND-type flash memory. The intermediate voltage that moderate, as much as possible, effects on the selected memory cell is applied to the unselected memory cells.